The invention relates to a device for dividing a pulse series by a predetermined factor, said device comprising input register means for storing a code word for controlling said predetermined factor, said input register means having a first input and furthermore a plurality of first outputs each for a bivalent signal, said device furthermore comprising a primary dividing means for dividing said pulse series by an integer, having second outputs for producing cycles of mutually time-shifted driving pulses thereon, said device furthermore comprising a multiplexing circuit having a plurality of second inputs each connected to a respective one of said first outputs and third inputs for receiving a second plurality of said driving pulses for gating each time a code bit to a common third output.
A circuit of this kind is known from U.S. Pat. No. 3,460,129. The known divider uses D-type flipflops and a multiplicity of interconnections making it useful only to relatively low operating frequencies. Typical upper limits for even the fastest logic ECL families are determined by switching speed limitations in the 500 Megabit/second range. Such a typical upper switching speed while satisfactory for use in systems for multiplexing signals on a coaxial cable which has a typical upper frequency limit of 560 Megabits/second, is of no avail when working at higher bit rates in optical fiber systems.